The present invention relates to an interface apparatus for connecting devices operating at different clock rates, and in particular to an interface apparatus for connecting a clocked device provided with an asynchronous bus to a clocked peripheral device provided with a synchronous bus. In addition, the present invention also relates to a method for operating such an interface apparatus.
Many digital processor devices like for example digital signal processors (hereinafter referred to as DSP) are provided with an asynchronous data bus which is controlled by timing control signals. In connection with such an asynchronous bus certain difficulties may arise in application situations which have strict timing requirements. For example, when a data bus of a DSP device has to be connected to an Application Specific Integrated Circuit device (hereinafter referred to as ASIC device), which uses only synchronous memory means controlled by a clock signal, timing and/or connection problems may arise.
According to a principle interface that is common to DSP processors of various manufacturers (like, e.g. processors of the DSPxe2x80x9416XX family manufactured by ATandT(copyright) or, as a further example, DSP processors provided by Texas Instruments(copyright)), an asynchronous data bus of a DSP is controlled by the following signals: signal ADDRESS: specifying the address of memory means (a memory or register) to which data signals DATA are to be written and/or read from; signal RWN (read/write): specifying that dependent on its currently set value (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d) the DSP processor performs a data transfer operation, i.e. either a write operation or a read operation to or from a peripheral circuit device like an ASIC device and the memory means provided therein; and signal ENA: specifying, dependent on its binary value, whether the DSP device carries out a read/write operation at all, i.e. indicating whether the DSP device is active (ENA=0) or inactive (ENA=1).
The DSP processor also provides a clock signal CKO which may be used for clocking the ASIC operation and also to control the interface. Nevertheless, a clock signal CLK for clocking the ASIC device could be generated elsewhere, such that clock signals supplied to the ASIC device (CLK) and the DSP device (CKO) originate from different sources, respectively. Then, the DSP device and the ASIC device can be independently clocked, and even clocked at different clock rates. Nevertheless, in such a case both devices (DSP and ASIC) could operate with the same clocks and could even be synchronous to each other. In this connection, it has to be noted that for simplified description, the signal CLK for clocking the ASIC device is described hereinafter as if being provided by the DSP device, while this does not limit the invention to such an arrangement.
A schematic block diagram of an ASIC device 3 as a device provided with synchronous memory means 3a being connected via an interface apparatus (I/F) 2 to a DSP device 1 provided with an asynchronous data bus (not shown) is depicted in FIG. 1.
Previously, several interface apparatuses have been proposed for the purpose of interconnecting a DSP device to an ASIC device.
For example, EP-A1-0 649 097 relates to a synchronous approach and discloses an interface between unsynchronized devices, which interface comprises a delay means for synchronizing the write strobe of the first device with the system clock of the second device.
Furthermore, another synchronous approach is proposed in WO-A-96/38793 of the present applicant. According to the method and apparatus for adapting an asynchronous bus to a synchronous circuit as disclosed therein, the timing control signals of the DSP data bus are synchronized to the system clock signal CLK using a flip-flop arrangement.
Moreover, apart from synchronous interfaces, a type of interfaces based on an asynchronous approach has been proposed by the present applicant. In particular, such an asynchronous interface is described in a recent Finnish patent application (FI 972091 filed May 15, 1997) of the same applicant, the present inventor being a co-inventor thereof. As disclosed therein, an asynchronous state machine creates additional signals for internal use in the interface apparatus and/or ASIC device, based on the supplied signals ENA and RWN. In particular, a signal that may be used for burst type read operations from a memory as a clock signal of, for example, an autoincrement counter is generated.
The above mentioned previous solutions, however, merely solved the problem of providing an asynchronous interface, while these solutions will no longer work reliably if the clock rate of the DSP device is much faster than the clock rate of the ASIC device. That is, problems caused due to different clock speeds between the DSP device and the ASIC device can not be prevented by these interface apparatuses.
For example, the DSP device clock frequency is suggested to be 90 MHz, while the ASIC device clock frequency is suggested to be 50 MHz. Since the DSP device may write data with nearly double speed as compared to the ASIC device reading speed, this means that for every writing operation period an extra period of no operation or a xe2x80x9cno operationxe2x80x9d instruction (hereinafter NOP period/instruction) is required.
This problem will become more and more severe in future when the processing capacity of the used DSP devices is overloaded and it is required to increase the clock frequency of the DSP devices without a possibility to increase the clock frequencies of ASIC devices used.
Stated in other words, timing problems become the more severe the greater the difference in clock frequencies between DSP device and the ASIC device to be connected thereto is.
FIG. 2 of the accompanying drawings represents a timing diagram of above mentioned signals according to the method previously proposed and as disclosed in WO-A-96/38793. In particular, FIG. 2 illustrates a situation, in which there occurs a problem upon connection of a digital ASIC device to a data bus of a DSP device, if the clock frequency of the ASIC device is significantly lower than the clock frequency of the DSP device. As already briefly explained further above, the signal ENA is the DSP device enable signal, indicative of whether the DSP device is active or not with regard to a data transfer operation, i.e. a writing/reading operation to/from the ASIC device; the signal RWN is the signal specifying the writing/reading operation when the DSP device is enabled; ADDRESS indicates the signal transmitted on the address bus of the DSP device; DATA represents the signal transmitted on the data bus of the DSP device; CLK is the system clock of the ASIC device (provided by the DSP device or from an independent external clock signal generating means, as mentioned above). These signals are provided and/or transmitted by the DSP device. Signals ADDRESS1, ADDRESS2, and DATA1, DATA2, indicate address and data values, respectively, applied to the ADDRESS and DATA signal lines, respectively, during periods, during which a specific data is to be written to and/or read from a corresponding specific address in a memory means.
The additionally depicted signal WR_ENABLE is an internal signal generated by the interface apparatus and used only internally within the ASIC device and the interface device. The signal WR_ENABLE actually enables the writing of transmitted data to a memory means of the ASIC device after synchronization.
As shown in the timing diagram, two subsequent writing operations are to be performed: writing DATA1 to ADDRESS1, followed by writing DATA2 to ADDRESS2. Writing is instructed when the signal ENA assumes a low value (xe2x80x9c0xe2x80x9d), thereby enabling the DSP device and when simultaneously the signal RWN assumes a low value (xe2x80x9c0xe2x80x9d), thereby instructing writing of data to a memory means. On the other hand, a pair of signal values (ENA, RWN)=(0, 1) represents a reading operation from a memory means, while signal values (ENA, RWN)=(1,X) represent a state in which the DSP device is inactive (disabled or idle, respectively, with xe2x80x9cXxe2x80x9d being a so-called xe2x80x9cDon""t carexe2x80x9d value for the signal RWN, which signal RWN is of no importance in case the DSP device is inactive).
Apparently, according to the previously proposed method, DATA1 and ADDRESS1 are latched in a respective data register and address register upon a change of at least one of the signals ENA, RWN to the high level or value (xe2x80x9c1xe2x80x9d). Therefore, at a point of time labeled t1 in FIG. 2 (at the end of a write instruction), the signals ADRESS1 and DATA1 can be assumed to be temporarily stored or latched, respectively. However, the generation of the internal signal WR_ENABLE for this first writing operation, is delayed due to the clocked flip-flop arrangement used for its generation, to thereby be synchronized to the clock signal CLK. Thus, the signal WR_ENABLE occurs at a point of time labeled t3 and shortly before the latching (time point labeled t2) of a pair of data ADRESS2, DATA2 of the subsequent (second) writing operation takes place.
Thus, the signal WR_ENABLE actually enabling the writing, i.e. the transfer of the latched data to memory means at the ASIC device side, is active when ADDRESS2, DATA2 are latched. Consequently, the writing of DATA1 at ADDRESS1 is failed and the writing of DATA2 at ADDRESS2 has been effected too early.
This is the reason for the provision of at least one extra period of no operation instruction cycles (NOP) between writing operations, as required by such previous solutions, and as required for example by the arrangement disclosed in WO-A-96/38793.
Thus, as DSP processor operation speed increases while the processing speed of an ASIC device connected thereto remains constant during the lifetime of the ASIC, a gain and benefit of an increase in the clock frequency of a DSP device will be lost because the interface to the ASIC device requires some NOP instructions between successive read and/or write operations. In addition, similar problems may manifest in case a device from which data are to be read provides the data much faster than a device reading the data can read the data.
It is therefore an object of the present invention to provide an interface apparatus for connecting a device provided with an asynchronous bus to a peripheral device provided with a synchronous bus as well as a method for operating such an interface apparatus, by means of which the gain and benefit of an increase in the clock frequency of an asynchronous device like a DSP device will not be lost because the interface apparatus to the ASIC device requires some NOP instructions between successive data transfer operations, i.e. read and/or write operations.
This object is achieved by an apparatus for transferring data between a first device and a memory area of memory means of a second device, the memory area being determined by an address, within a system which comprises at least one system clock and in which the first device provides at least a signal indicating data transfer and a signal indicating the direction of data transfer, the apparatus comprising buffer registers for temporarily storing the data to be transferred and the address of the memory area to and/or from which the data are to be transferred, and a control means for controlling said buffer registers to temporarily store said data and address to be transferred in response to the signal indicating that data transfer being active and the signal indicating the direction of data transfer between the first device and the second device, the signals thereby instructing either a write operation or a read operation, characterized by at least two groups of buffer registers for storing data and associated addresses transmitted in consecutive data transfer operations, and in that said control means is adapted to generate a control signal for alternately switching between a first group of buffer registers and a second group of buffer registers of said at least two groups of buffer registers after each of a respective one of consecutive data transfer operations.
Moreover, this object is achieved by a method for transferring data between a first device and a memory area of memory means of a second device, the memory area being determined by an address, within a system which comprises at least one system clock and in which the first device provides at least a signal indicating data transfer and a signal indicating the direction of data transfer, the method comprising the steps of temporarily storing the data to be transferred and the address of the memory area to and/or from which the data are to be transferred in buffer registers, and controlling said buffer registers by means of a control means, to temporarily store said data and address to be transferred in response to the signal indicating that data transfer being active and the signal indicating the direction of data transfer between the first device and the second device, the signals thereby instructing either a write operation or a read operation, characterized by the further steps of providing at least two groups of buffer registers for storing data and associated addresses transmitted in consecutive data transfer operations, generating by means of said control means a control signal for alternately switching between a first group of buffer registers and a second group of buffer registers of said at least two groups of buffer registers after each of a respective one of consecutive data transfer operations.
Advantageous further developments of the present invention are as set out in the respective dependent claims.
In particular, the interface apparatus according to the present invention and the method according to the present invention for operating the same provide the advantage that a simple and reliable control of data transfer operations (reading/writing) is achieved.
Moreover, in contrast to previous solutions which set quite critical requirements for clock frequency ratios for a DSP device and an interface to an ASIC device, according to the present invention, this is no more critical.
This may be even further advantageous if a DSP device uses different clock signals than the ASIC device connected thereto. In this case it is possible to design a system which allows an easy upgrade of a faster processor device without having to worry about a speed upgrade of the ASIC device, while there is also no need for the provision of extra NOP instructions after a speed upgrade of a DSP device.
In addition, by using the proposed method according to the present invention and the circuitry of the apparatus according to the present invention, the formerly required cycles for performing NOPs, i.e. wasted and/or lost cycles of processor time during which no operation was performed, can now be used again for calculation purposes by the DSP device, so that the advantage resulting from a higher clock frequency has not to be sacrificed to NOP instruction cycles.
Furthermore, in case of a writing data transfer, since in the end of every write operation by the DSP device the additionally internally generated ENABLE signal is forced to change its value, always the correct data will be connected to the memory means specified by the correct address, without any additional NOP cycle between successive writing operations being necessary.